1. Field of the Invention
The present invention relates to a semiconductor device having a multilevel interconnection and a method for manufacturing the semiconductor device.
2. Description of the Related Art
Multilevel interconnections have been developed so as to improve the integration density and the operation speed of semiconductor devices. Instead of aluminum interconnects used in earlier stage of semiconductor technology, copper interconnects with higher tolerable current density and higher melting point than those of aluminum interconnects have been developed for achieving lower wiring resistance and increasing current density and reliability of the interconnection.
Nevertheless, failures due to increase in interconnect resistance and disconnection caused by stress migration have occurred in a semiconductor device including copper interconnects.
“The stress migration” is a phenomenon in which metallic atoms in metallic interconnects move so as to reduce a stress that is applied to the metallic interconnects due to the difference in thermal expansion coefficients between the metallic interconnects and interlevel insulator layers surrounding the metallic interconnects. FIGS. 1 and 2 show a semiconductor device having a first level interconnect 13 and a second level interconnect 15 formed with a copper film, respectively, and a connecting via-plug 31 implemented by a copper film. In FIG. 1, which shows a top view, a second interlevel insulator 14 (shown in FIG. 2) is not shown, however, the connecting via-plug 31 is shown as if the second level interconnect 15 is transparent. The following other top views pertaining to the embodiments of the present invention are represented in the same manner to avoid cluttering up the drawings, although there may be a plurality of upper interlevel insulators actually. In addition, in FIG. 1, “a void 39” generated by stress migration is represented by broken line as if the second level interconnect 15 is transparent. FIG. 2 is a cross-sectional view taken on line II—II, cutting along the direction on which the first level interconnect 13 extends as shown in FIG. 1. In the semiconductor device shown in FIGS. 1 and 2, a void 39 is generated due to stress migration on the top surface of the first level interconnect 13 especially at the interface between the connecting via-plug 31 and the first level interconnect 13. This is because a strong stress is applied to the interface between the connecting via-plug 31 and the first level interconnect 13 during a via formation process and an interconnect formation process.
As described above, there have been problems such as increase in resistance between interconnect layers and disconnection failures due to the void 39 generated by stress migration.